Introduction to SoCs with the Xilinx Zynq 7000 Series

Topics Covered during this Course

• Xilinx Zynq SoC Architecture
• Designing custom AXI Wrappers for custom IP for use by processing elements
• Baremetal C interfaces from ARM Cortex A-9 and Microblaze soft processors to custom IP
• Custom cryptographic accelerator IP
• Designing acceleration blocks using Vivado HLS
• Overview of Linux interfaces to custom FPGA designs

Day 1

• Theory: Building custom SoC with Zynq
• Overview of Zynq 7000
• Multicore Architectures
• Integrating custom IP into an SoC
• Workflow best practices
• OS selection: while(1) OS vs RTOS vs Linux

Assignment 1: Cortex A-9 hard peripherals baremetal

• Students will bring up a baremetal hello world example using the processing system UART
• Students will use Vivado and Vitis to create a design and load their software
• Assignment 2: XADC Integration
• Students will instatatie the XADC macro in the Programmable Logic
• Next students will create use the AXI bus to connect XADC to the Processing system
• Lastly, they will integrate the XADC driver to constantly print out XADC parameters

Assignment 3: Multi-core message passing

• Students will add a microblaze soft core processor to their design
• Students will design a protocol for message passing between the two cores
• Then they send messages from the ARM the microblaze and back where the microblaze responds with hello world

Assignment 4: Cryptographic co-processor

• With the ARM and the microblaze, the microblaze will implement a cryptographic algorithm in software.
• Students will send messages over the mailbox IP to perform crypto, send it to the cryptographic function and return the result.

Day 2

Assignment 5: Vivado HLS

• Students will build a hashing core in C and then synthesize it using Vivado HLS.
• Students will make a custom IP core using an AXI 4 Lite interface
• Finally, they will add the hash core and implement a driver from the microblaze and compare the performance of software vs hardware implementations.
• Theory: Picoblaze 8-bit softcore
• Overview of the picoblaze 8-bit soft core processor architecture
• Discuss when to use a picoblaze vs a microblaze
• Development for picoblaze assembly

Assignment 6: Picoblaze Finite State Machine

• Students will add a Finite State Machine to control the usage of the crypto core
• Students will use the FSM to also control the LEDs on the Arty
• Lastly, students will integrate the completed design using an ARM core, Microblaze core, and a picoblaze core.
• Theory: Embedded Linux
• Overview of embedded Linux architecture
• How build systems work for embedded Linux
• Boot process and hardware initialization

Assignment 7: Integration with Embedded Linux

• Students will be given an SD card image with a compiled Linux image and their bitstream
• Students will discover and understand the boot flow from the first stage boot loader, to uboot, to the kernel and mounting of the filesystems.
• Lastly, students will write a user space driver to interface with the hardware they previously built

Class Requirements

• A laptop/desktop capable of running VMWare and at least 50GB of available storage
• Students must purchase and use their own Arty Z7 Zynq-7020