Large SoC Development with the Xilinx Zynq Ultrascale+ MPSoC

This is the introductory course to the Secure Embedded Development with Zynq UltraScale series. Zynq UltraScale is a sophisticated multi-platform System-on-Chip that can enable many secure applications. This series focuses on the security aspects of the UltraScale devices. It is designed to teach students new to Xilinx UltraScale the workflow and tools in the intro class and work up to using the built-in security technologies in the later classes.

Topics Covered during this Course

• Xilinx Zynq UltraScale+™ MPSoC Architecture
• Adding custom IP to Zynq Designs
• Accelerating designs in C using Vivado HLS
• Building cryptographic accelerators (hashing cores)
• Benchmarking performance for software, HLS-generated, and custom verilog cores

Day 1 - HW Engineer Day

• Theory: Zynq UltraScale Overview
• AXI overview: AXI Streaming vs Full AXI vs AXI lite
• Multicore Architectures
• Integrating custom IP into an SoC
• Workflow best practices

Assignment 1:Introduction to Vivado

• Students will create a basic Hello World design implemented in Vivado
• Students will understand and will perform flashing of the design to their board and how to use the hardware manager in Vivado
• Finally, students will becoming comfortable with adding custom IP blocks to their design, building the bitstream and exporting the project to other tools

Assignment 2:Integrating custom verilog into the block design

• Students will implement a custom verilog module and add it to the block design
• Students that have taken our Intro to FPGA class (or know verilog) will be able to implement the block design in verilog, if not, the verilog will be provided to the students.
• We will integrate the verilog into the block design.

Assignment 3:Building and adding custom IP

• Students will create a custom IP (from verilog) using the IP Integrator
• We will add the core to the project and simulate it to verify basic tests
• Students will then take the core, add it to their IP repo, and integrate it to their project

Assignment 4: Vivado HLS

• Students will build a hashing core in C and then synthesize it using Vivado HLS.
• Students will make a custom IP core using an AXI 4 Lite interface
• Students will run hardware-software co-simulator to ensure their core works and export the core into their IP repo (which will be used on day 2).

Day 2 - SW Engineer Day

• SW Development workflows
• Multicore Debugging
• Writing drivers for custom hardware

Assignment 5:Introduction to Vitis

• Vitis is Xilinx latest software development tool new in 2019. We will exclusively be using Vitis for ZynqMP bare-metal software development.
• We will discuss the Vitis development workflows
• Students learn how to make projects in Vitis from their custom hardware.
• We will write a simple Hello World bare-metal C application on one of the Cortex-A cores.

Assignment 6: Multi-core message passing between the A53

• Students will develop a protocol for multi-core message passing.
• Using some of the hard-cores, students add the necessary internal buses and IP blocks to provide message passing capabilities
• Students will implement the message passing in baremetal C using their design

Assignment 7: SHA256 hash benchmark on baremetal C

• Using the multi-core setup, students will implement SHA256 in software
• They will then create a driver to send a message to the second core, hash it, and get the result
• Students will collect benchmarks for SHA256 implemented in software

Assignment 8: SHA256 hash benchmark from Vivado HLS core

• Students will write a driver for their Vivado HLS SHA256 core using AXI lite.
• We will learn the common AXI4LITE pattern of controlling IP cores.
• Students will use the memory mapped I/O to control the core.
• They will compare the benchmarks from the software implementation and their vivado HLS implementation

Assignment 9: SHA256 hash benchmark from true verilog core

• Students will write a driver for their SHA256 core in verilog
• They will compare the benchmarks from the software implementation, vivado HLS, and custom verilog
• We will discuss the tradeoffs between all three implementations comparing various security features like performance, key isolation, and internal SoC key management

Class Requirements

A laptop/desktop capable of running VMWare and at least 50GB of available storage Students must purchase and use their own Utlra96 board and accessories. This kit will be used in the entire Ultrascale development series courses.

• Ultra96-V2 Zynq Board
• Ultra96 JTAG Adapter
• Ultra96 Power Supply for US/EU/UK/AU